Static random access memories (“SRAM”) include a plurality of bit cells disposed in rows and columns to form an array. Each SRAM bit cell includes a plurality of transistors coupled to bit lines and word lines that are used to read one or more bits of data from and write one or more bits of data to the bit cell. SRAMs have the advantageous feature of holding data without requiring a refresh and are commonly used in integrated circuits. Embedded SRAM is particularly popular in high speed communication, image processing and system on chip (SOC) applications.
Dual port SRAM bit cell is a specific type of SRAM bit cell having two ports (e.g., port A and port B) that enable multiple reads or writes of the bits of data stored in the SRAM bit cell to occur via port A and port B at approximately the same time. Such dual-port bit cell design allows for parallel operations to be performed on the bit cell by different applications. Moreover, if a first SRAM cell and a second SRAM cell are in a same column or a same row, a read operation to the first SRAM cell can also be performed simultaneously with a write operation on the second SRAM cell.